Lattice Semiconductor Continues to Bolster Design Tool Suites for Low-Power, Small Form Factor FPGAs

By CIOReview Team

Lattice Semiconductor Corporation (NASDAQ: LSCC), the leading provider of customizable smart connectivity solutions, recently announced availability of an updated version of its Lattice Diamond® design tool suite, version 3.7. It includes support for more Lattice devices as well as performance improvements to help customers design solutions based on Lattice FPGAs with the lowest possible size, power consumption and cost.

Lattice Diamond design software is a complete suite of FPGA tools with an easy-to-use interface, efficient design flow, superior design exploration and more. Key new features in version 3.7 include support for the expanded ECP5™ and MachXO2™/MachXO3™ FPGA families.

  • Latest software updates for ECP5-5G™ family, the first FPGA family to support 5G SERDES and up to 85K LUTs in a small 10x10 mm package. Click here to request a license to access ECP5-5G devices in the software.
  • Software support for new ECP5 12K device that enables cost optimized programmable IO bridging functionality in a variety of end markets.
  • Software support for enhanced features in MachXO2 and MachXO3 FPGAs including low-voltage I/O support, password protection against malicious erase commands, and soft error detection and correction support (SED/SEC).
  • Support for new MachXO2 QFN32 package to implement functionality such as power management, bridging and signal aggregation in a variety of Industrial applications.
  • Improvements to the Lattice Synthesis Engine (LSE) used in the tool suite allow for smaller footprint and design productivity.

“The small size, low power consumption and high performance of our FPGA families make them the ideal connectivity solution for consumer, industrial and communications applications,” said Hua Xue, vice president, software systems and solutions at Lattice Semiconductor. “With these updates to our popular Lattice Diamond software suite, our customers will be able to achieve their design goals without compromising device functionality.”

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